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To analyze two‐phase flow in micro‐channel heat exchangers used for high flux micro‐electronics cooling and to obtain performance parameters such as thermal resistance, pressure drop, etc. Both uniform and non‐uniform micro‐channel base heat fluxes are considered.

Energy balance equations are developed for two‐phase flow in micro‐channels and are solved using the finite element method (FEM). A unique ten noded element is used for the channel descritization. The formulation also automatically takes care of single‐phase flow in the micro‐channel.

Micro‐channel wall temperature distribution, thermal resistance and the pressure drop for various uniform micro‐channel base heat fluxes are obtained, both for single‐ and two‐phase flows in the micro‐channel. Results are compared against data available in the literature. The wall temperature distribution for a particular case of non‐uniform base heat flux is also obtained.

The analysis is done for a single micro‐channel and the effects of multiple or stacked channels are not considered. The analysis needs to be carried out for higher heat fluxes and the validity of the correlation needs to be ascertained through experimentation. Effects of flow mal‐distribution in multiple channels, etc. need to be considered.

The role of two‐phase flow in micro‐channels for high flux micro‐electronics cooling in reducing the thermal resistance is demonstrated. The formulation is very useful for the thermal design and management of microchannels with both single‐ and two‐phase flows for either uniform or non‐uniform base heat flux.

A simple approach to accurately determine the thermal resistance in micro‐channels with two‐phase flow, for both uniform and non‐uniform base heat fluxes is the originality of the paper.

To provide some new and additional data for the design of a triple stack cold plate.

A detailed finite element formulation for the triple stack cold plate with and without heat losses from the top and bottom surfaces of the stack is presented to determine its performance under steady as well as unsteady conditions. The effects of the number of unit cells, different heat losses as well as the governing dimensionless parameter, M (involving stack dimension, properties of the stack material and the variation in the heat transfer coefficient) on the performance of the stack are investigated. The detailed formulation of the asymptotic waveform evaluation scheme is also given and applied to determine the transient performance of the stack.

The methods of analysis described are quite simple to use to determine the steady and unsteady performance of the triple stack cold plate under different operating conditions. The heat losses from the top and bottom surfaces of the stack do affect the maximum temperature of the stack and in such case, the assembled stack should be analysed.

The analysis is limited to an incompressible fluid. The effect of varying mass flow rate of the fluid in the stack passages is also not considered.

New and additional generated data will be helpful in the design of cold plates used in the cooling of electronic components.

The asymptotic waveform evaluation scheme is used for the first time to determine the transient performance of the triple stack cold plate under different operating conditions. The results thus obtained are compared well with those found from the finite element analysis (FEM), but the computational effort and time required in the analysis is much small as compared to those required in the FEM analysis.

To determine the optimal dimensions for a stacked micro‐channel using the genetic algorithms (GAs) under different flow constraints.

GA is used as an optimization tool for optimizing the thermal resistance of a stacked micro‐channel under different flow constraints obtained by using the one dimensional (1D) and two dimensional (2D) finite element methods (FEM) and by thermal resistance network model as well (proposed by earlier researcher). The 2D FEM is used to study the effect of two dimensional heat conduction in the micro‐channel material. Some parametric studies are carried out to determine the resulting performance of the stacked micro‐channel. Different number of layers of the stacked micro‐channel is also investigated to study its effect on the minimum thermal resistance.

The results obtained from the 1D FEM analysis compare well with those obtained from the thermal resistance network model. However, the 2D FEM analysis results in lower thermal resistance and, therefore, the importance of considering the conduction in two dimensions in the micro‐channel is highlighted.

The analysis is valid for constant properties fluid and for steady‐state conditions. The top‐most surfaces as well as the side surfaces of the micro‐channel are considered adiabatic.

The method is very useful for practical design of micro‐channel heat‐sinks.

FEM analyses of stacked micro‐channel can be easily implemented in the optimization procedure for obtaining the dimensions of the stacked micro‐channel heat‐sinks for minimum thermal resistance.

The purpose of this paper is to apply asymptotic waveform evaluation (AWE) to the transient analysis of a two‐layered counter‐flow microchannel heat sink.

A two‐layered counter‐flow microchannel heat sink in both steady state and transient conditions is analysed. Finite element analysis is used in the steady state analysis whereas AWE is used in the transient analysis.

A two‐layered microchannel produces different temperature distribution compared to that obtained for a single‐layered microchannel. The maximum temperature occurs at the middle of the bottom wall whereas the maximum temperature of a single‐layered microchannel is at the outlet of the bottom wall. The time taken to reach steady state is also investigated for different coolant flow rate and heat flux boundary conditions. It is observed that when fluid velocity increases, the time taken to reach steady state decreases, however, when the heat flux increases, the time taken to reach steady state does not change.

The fluid is incompressible and does not undergo phase change. The use of AWE provides an alternative method in solving heat transfer problem.

New and additional data will be useful in the design of a microchannel heat sink for the purpose of cooling of electronic components.

AWE is widely used in analyses of signal delays in electronic circuits, and rarely applied to mechanical systems. The present study applies AWE to heat transfer problems, and reveals that it reduces the computational time considerably. The results obtained are compared with conventional methods available in the literature, and they show good agreement. Hence the computational time is reduced, and the accuracy of results is verified.

Heat exchangers are devices for exchanging energy between two or more fluids. They find applications in various industries like power, process, electronics, refining, cryogenics, chemicals, metals and manufacturing sector. Even though heat exchanger designs have been reported quite extensively, they are generally limited to steady‐state performance, single phase fluids, a few of the many possible flow arrangements and only two fluid heat exchangers. While these designs encompass the majority of the heat exchanger applications, there are some designs, which involve several fluids such as in cryogenics or fault‐tolerant heat exchangers. The governing differential equations for a three‐fluid heat exchanger are written based on the conservation of energy. The finite element method is used to solve the governing differential equations along with the appropriate boundary conditions. The case of a Buoyonet heat exchanger (used for pasteurizing milk) is analysed and the results are compared with the analytical solution available in the literature. The Buoyonet heat exchanger, treated as a three‐fluid heat exchanger is also analysed. The effect of heat loss to the ambient from a parallel flow double pipe heat exchanger is also investigated and the results are compared with those available in the literature. The results are presented both in terms of the temperature distribution along the length of the heat exchanger and the variation of effectiveness with NTU. The methodology presented in this paper can be extended to heat exchangers with any number of streams and any combination of the flow arrangements.

This paper describes a generalized method of predicting the temperature distribution of the silicon chip with non‐uniform power dissipation patterns using Lagrangian interpolation function. A simplified heat sink thermal design was modeled to simulate a typical thermal design of microprocessor. Key thermal design parameters investigated are the heat source placement distance and level of heat dissipation. Verification of the proposed method was carried out by comparing the results with FEA predictions. Results of the verification show that the proposed method is reasonably accurate for practical purposes. A successful attempt has been made to predict the junction temperature of silicon chip with non‐uniform power distribution in a simple way.

Aims to present a finite element analysis based methodology for estimating the characteristic fatigue life of a solder joint interconnect under accelerated temperature cycling to predict the reliability performance of a flip chip package.

The method uses the ANSYSTM finite element analysis tool along with Anand's viscoplastic constitutive law. Darveaux's crack growth rate model was applied to calculate solder joint characteristic life using simulated viscoplastic strain energy density results at the package substrate and printed circuit board solder joints. Two package configurations are evaluated with the above methodology, with the first being a simplified flip chip model and the second being a detailed flip chip model. Each of these configurations is subjected to two accelerated temperature cycling tests.

Generally, the results indicate that the solder joint at the corner end of the package tends to fail first. The characteristic lives of solder joint at the package ball/board interface are 24‐46 percent higher than the characteristic lives of solder joint at the package ball/substrate interface. This means that the interface between the solder ball and substrate will fail first before the interface between the solder ball and the board.

Demonstrates that genetic algorithms can be used as tools to predict possible package dimensional values for given constraints on solder joint life.

To find the optimal geometries of rectangular and cylindrical fins for maximum heat dissipation.

The objective function for finding the optimized profiles of fins are solved by using the genetic algorithms (GAs). A range of fin shapes are investigated and the optimum solutions for various profile area are obtained.

Provide information to thermal engineers to what extent any particular extended surface or fin arrangements could improve heat dissipation from a surface to the surrounding fluid. Smaller fin volume in fin design is preferable as the heat is dissipated more effectively.

A new method of using GA for optimization of fins is used here. The value of this paper lies in providing data for selecting suitable fins for thermal management in electronic systems.

Limited to cases where the correlations for heat transfer coefficients are valid.

A very useful finding for practising thermal engineer especially in the area of electronic packaging as the parameters for the fin design can easily be found for any chosen profile area.

This paper's purpose is to review the design of a flip chip thermal test vehicle.

Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn‐in simulation are outlined and the design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. The design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also explained.

Describes the design considerations and processes of the package substrate and printed‐circuit board with special emphasis on the physical routing of the thermal test chip structures. These design processes are supported with thermal data from various finite‐element analyses carried out to evaluate the capability and limitations of thermal test vehicle design.

The validation and calibration procedures of a thermal test vehicle are presented in this paper.

This paper presents the thermal analyses carried out to predict the temperature distribution of the silicon chip with non‐uniform power dissipation patterns and to determine the optimal locations of power generating sources in silicon chip design layout that leads to the desired junction temperature, T_j. Key thermal parameters investigated are the heat source placement distance, level of heat dissipation, and magnitude of convection heat transfer coefficient. Finite element method (FEM) is used to investigate the effect of the key parameters. From the FEM results, a multiple linear regression model employing the least‐square method is developed that relates all three parameters into a single correlation which would predict the maximum junction temperature, T_j,max.